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| INTEGRATED CIRCUITS DATA SHEET For a complete data sheet, please also download: * The IC06 74HC/HCT/HCU/HCMOS Logic Family Specifications * The IC06 74HC/HCT/HCU/HCMOS Logic Package Information * The IC06 74HC/HCT/HCU/HCMOS Logic Package Outlines 74HC/HCT354 8-input multiplexer/register with transparent latches; 3-state Product specification File under Integrated Circuits, IC06 December 1990 Philips Semiconductors Product specification 8-input multiplexer/register with transparent latches; 3-state FEATURES * Transparent data latches * Transparent address latch * Easily expanding * Complementary outputs * Output capability: bus driver * ICC category: MSI GENERAL DESCRIPTION The 74HC/HCT354 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL QUICK REFERENCE DATA GND = 0 V; Tamb = 25 C; tr = tf = 6 ns 74HC/HCT354 (LSTTL). They are specified in compliance with JEDEC standard no. 7A. The 74HC/HCT354 data selectors/multiplexers contain full on-chip binary decoding, to select one-of-eight data sources. The data select address is stored in transparent latches that are enabled by a LOW on the latch enable input (LE). The transparent 8-bit data latches are enabled when the active LOW data enable input (E) is LOW. When the output enable input OE1 = HIGH, OE2 = HIGH or OE3 = LOW, the outputs go to the high impedance OFF-state. Operation of these output enable inputs does not affect the state of the latches. TYPICAL SYMBOL tPHL/ tPLH PARAMETER propagation delay Dn, E to Y, Y Sn, LE to Y, Y CI CPD Notes 1. CPD is used to determine the dynamic power dissipation (PD in W): PD = CPD x VCC2 x fi + (CL x VCC2 x fo) where: fi = input frequency in MHz fo = output frequency in MHz (CL x VCC2 x fo) = sum of outputs CL = output load capacitance in pF VCC = supply voltage in V 2. For HC the condition is VI = GND to VCC For HCT the condition is VI = GND to VCC - 1.5 V ORDERING INFORMATION See "74HC/HCT/HCU/HCMOS Logic Package Information". input capacitance power dissipation capacitance per latch notes 1 and 2 CONDITIONS HC CL = 15 pF; VCC = 5 V 20 24 3.5 68 22 27 3.5 71 ns ns pF pF HCT UNIT December 1990 2 Philips Semiconductors Product specification 8-input multiplexer/register with transparent latches; 3-state PIN DESCRIPTION PIN NO. 8, 7, 6, 5, 4, 3, 2, 1 9 10 11 14, 13, 12 15, 16 17 18 19 20 SYMBOL D0 to D7 E GND LE S0, S1, S2 OE1, OE2 OE3 Y Y VCC NAME AND FUNCTION data inputs data enable input (active LOW) ground (0 V) address latch enable inputs (active LOW) select inputs output enable input (active LOW) output enable input (active HIGH) 3-state multiplexer output (active LOW) 3-state multiplexer output (active HIGH) positive supply voltage 74HC/HCT354 Fig.1 Pin configuration. Fig.2 Logic symbol. Fig.3 IEC logic symbol. December 1990 3 Philips Semiconductors Product specification 8-input multiplexer/register with transparent latches; 3-state FUNCTION TABLE INPUTS ADDRESS (1) S2 X X X L L L L H H H H L L L L H H H H Notes X X X L L H H L L H H L L H H L L H H S1 X X X L H L H L H L H L H L H L H L H S0 E X X X L L L L L L L L H H H H H H H H H X X L L L L L L L L L L L L L L L L OUTPUT ENABLE OE1 X H X L L L L L L L L L L L L L L L L OE2 X X L H H H H H H H H H H H H H H H H OE3 Y Z Z Z D0 D1 D2 D3 D4 D5 D6 D7 D0n D1n D2n D3n D4n D5n D6n D7n Y Z Z Z D0 D1 D2 D3 D4 D5 D6 D7 D0n D1n D2n D3n D4n D5n D6n D7n OUTPUTS 74HC/HCT354 DESCRIPTION outputs in high impedance OFF-state data latch is transparent data is latched 1. This column shows the input address set-up with LE = LOW (address latch is transparent). 2. D0 to D7 = data at inputs D0 to D7 D0n to D7n = data at inputs D0 to D7 before the most recent LOW-to-HIGH transition of E H = HIGH voltage level L = LOW voltage level X = don't care Z = high impedance OFF-state December 1990 4 Philips Semiconductors Product specification 8-input multiplexer/register with transparent latches; 3-state 74HC/HCT354 Fig.4 Functional diagram. December 1990 5 Philips Semiconductors Product specification 8-input multiplexer/register with transparent latches; 3-state 74HC/HCT354 Fig.5 Logic diagram. December 1990 6 Philips Semiconductors Product specification 8-input multiplexer/register with transparent latches; 3-state DC CHARACTERISTICS FOR 74HC For the DC characteristics see "74HC/HCT/HCU/HCMOS Logic Family Specifications". Output capability: bus driver ICC category: MSI AC CHARACTERISTICS FOR 74HC GND = 0 V; tr = tf = 6 ns; CL = 50 pF Tamb (C) 74HC SYMBOL 74HC/HCT354 TEST CONDITIONS WAVEFORMS UNIT V CC (V) ns 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 Fig.7 PARAMETER min. +25 -40 to +85 -40 to +125 min. max. typ. max. min. max. tPHL/ tPLH propagation delay Dn to Y, Y tPHL/ tPLH propagation delay E to Y, Y tPHL/ tPLH propagation delay Sn to Y, Y tPHL/ tPLH propagation delay LE to Y, Y tPZH/ tPZL 3-state output enable time OEn to Y, Y tPZH/ tPZL 3-state output enable time OE3 to Y, Y tPHZ/ tPLZ 3-state output disable time OEn to Y, Y tPHZ/ tPLZ 3-state output disable time OE3 to Y, Y tTHL/ tTLH output transition time 61 22 18 63 23 18 77 28 22 77 28 22 39 14 11 44 16 13 50 18 14 55 20 16 14 5 4 80 16 14 17 6 5 17 6 5 210 42 36 250 50 43 260 52 44 290 58 49 125 25 21 135 27 23 155 31 26 155 31 26 60 12 10 100 20 17 100 20 17 265 53 45 315 63 54 325 65 55 365 73 62 155 31 26 170 34 29 195 39 33 195 39 33 75 15 13 120 24 20 120 24 20 315 63 54 375 75 64 390 78 66 435 87 74 190 38 32 205 41 35 235 47 40 235 47 40 90 18 15 ns Fig.6 ns Fig.8 ns Fig.9 ns Fig.10 ns Fig.10 ns Fig.10 ns Fig.10 ns Figs 7, 8 and 9 tW data enable pulse width E LOW ns Fig.6 tW latch enable pulse width LE 80 LOW 16 14 ns Fig.9 December 1990 7 Philips Semiconductors Product specification 8-input multiplexer/register with transparent latches; 3-state Tamb (C) 74HC SYMBOL 74HC/HCT354 TEST CONDITIONS UNIT V WAVEFORMS CC PARAMETER min. +25 -40 to +85 -40 to +125 min. max. (V) ns 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 Fig.10 typ. max. min. max. tsu set-up time Dn to E set-up time Sn to LE hold time Dn to E hold time Sn to LE 50 10 9 50 10 9 5 5 5 5 5 5 11 4 3 14 5 4 -6 -2 -2 -8 -3 -2 65 13 11 65 13 11 5 5 5 5 5 5 75 15 13 75 15 13 5 5 5 5 5 5 tsu ns Fig.10 th ns Fig.11 th ns Fig.10 December 1990 8 Philips Semiconductors Product specification 8-input multiplexer/register with transparent latches; 3-state DC CHARACTERISTICS FOR 74HCT For the DC characteristics see "74HC/HCT/HCU/HCMOS Logic Family Specifications". Output capability: bus driver ICC category: MSI Note to HCT types 74HC/HCT354 The value of additional quiescent supply current (ICC) for a unit load of 1 is given in the family specifications. To determine ICC per input, multiply this value by the unit load coefficient shown in the table below. INPUT Dn, Sn OE3 LE E, OEn UNIT LOAD COEFFICIENT 0.2 0.25 0.5 1.0 December 1990 9 Philips Semiconductors Product specification 8-input multiplexer/register with transparent latches; 3-state AC CHARACTERISTICS FOR 74HCT GND = 0 V; tr = tf = 6 ns; CL = 50 pF Tamb (C) 74HCT SYMBOL PARAMETER min. 74HC/HCT354 TEST CONDITIONS WAVEFORMS UNIT V CC (V) ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 4.5 4.5 4.5 4.5 4.5 4.5 4.5 4.5 4.5 4.5 4.5 4.5 4.5 4.5 4.5 Fig.7 Fig.6 Fig.8 Fig.9 Fig.10 Fig.10 Fig.10 Fig.10 Figs 7, 8 and 9 Fig.6 Fig.9 Fig.11 Fig.10 Fig.11 Fig.10 +25 -40 to +85 -40 to +125 min. max. 71 81 89 95 51 51 50 59 18 24 24 15 15 14 14 typ. max. min. max. tPHL/ tPLH tPHL/ tPLH tPHL/ tPLH tPHL/ tPLH tPZH/ tPZL tPZH/ tPZL tPHZ/ tPLZ tPHZ/ tPLZ tTHL/ tTLH tW tW tsu tsu th th propagation delay Dn to Y, Y propagation delay E to Y, Y propagation delay Sn to Y, Y propagation delay LE to Y, Y 3-state output enable time OEn to Y, Y 3-state output enable time OE3 to Y, Y 3-state output disable time OEn to Y, Y 3-state output disable time OE3 to Y, Y output transition time data enable pulse width E LOW latch enable pulse width LE LOW set-up time Dn to E set-up time Sn to LE hold time Dn to E hold time Sn to LE 16 16 10 10 9 9 25 26 30 31 18 18 18 21 5 6 6 4 5 0 -3 47 54 59 63 34 34 33 39 12 20 20 13 13 11 11 59 68 74 79 43 43 41 49 15 December 1990 10 Philips Semiconductors Product specification 8-input multiplexer/register with transparent latches; 3-state AC WAVEFORMS 74HC/HCT354 (1) HC : VM = 50%; VI = GND to VCC. HCT: VM = 1.3 V; VI = GND to 3 V. Fig.6 Waveforms showing the data enable input (E) pulse width, the data enable to output (Y, Y) propagation delays, and the output transition times. (1) HC : VM = 50%; VI = GND to VCC. HCT: VM = 1.3 V; VI = GND to 3 V. Fig.7 Waveforms showing the data input (Dn) to output (Y, Y) propagation delays and the output transition times (E = LOW). December 1990 11 Philips Semiconductors Product specification 8-input multiplexer/register with transparent latches; 3-state 74HC/HCT354 (1) HC : VM = 50%; VI = GND to VCC. HCT: VM = 1.3 V; VI = GND to 3 V. Fig.8 Waveforms showing the select input (Sn) to output (Y, Y) propagation delays and the output transition times (LE = LOW). (1) HC : VM = 50%; VI = GND to VCC. HCT: VM = 1.3 V; VI = GND to 3 V. Fig.9 Waveforms showing the address latch enable input (LE) pulse width, the address latch enable input to output (Y, Y) propagation delays and the output transition times. December 1990 12 Philips Semiconductors Product specification 8-input multiplexer/register with transparent latches; 3-state 74HC/HCT354 (1) HC : VM = 50%; VI = GND to VCC. HCT: VM = 1.3 V; VI = GND to 3 V. Fig.10 Waveforms showing the set-up and hold times for the select input (Sn) to the address latch enable input (LE). (1) HC : VM = 50%; VI = GND to VCC. HCT: VM = 1.3 V; VI = GND to 3 V. Fig.11 Waveforms showing the set-up and hold times for the data input (Dn) to the data enable input (E). (1) HC : VM = 50%; VI = GND to VCC. HCT: VM = 1.3 V; VI = GND to 3 V. Fig.12 Waveforms showing the 3-state enable and disable times. December 1990 13 Philips Semiconductors Product specification 8-input multiplexer/register with transparent latches; 3-state PACKAGE OUTLINES See "74HC/HCT/HCU/HCMOS Logic Package Outlines". 74HC/HCT354 December 1990 14 |
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